“Architecture and FPGA Implementation of a Digit-Serial RSA Processor”

this paper we present an innovative hardware architecture and an FPGA-based implementation of the Montgomery's algorithm based on a digit-serial approach, which allows the basic arithmetic operations to be broken into words and processed in a serialized fashion. As a consequence, the architecture implementation takes advantage of a short critical path and low area requirements. In fact, as compared to other solutions in the literature, the proposed implementation of the RSA processor has smaller area requirements and comparable performance. The serialization factor S of our serial architecture is taken as a parameter and the final performance level is given as a function of this factor. We thoroughly explore the design tradeo#s, in terms of area requirements vs time performance, for di#erent values of the key length and the serialization factor